EEPROMs (electrically erasable programmable read only memories) have become popular for storing information and retaining data even without power being supplied to a device. Retention of data across power cycles makes an EEPROM popular in consumer electronics products. EEPROMs are used in a broad spectrum of consumer, automotive, telecommunication, medical, industrial and PC related markets. The EEPROM is primarily used to store personal preference, configuration, and setup data in electronic systems. Not needing power supply support for memory retention means that EEPROMs offer a lower pin count, smaller packages, lower voltages, as well as lower power consumption compared to memory devices requiring constant power and refreshing of storage contents.
With reference to FIG. 1a, a bitline BL connects to an electrically alterable memory cell 100 in a prior art schematic diagram of an electrically alterable memory cell array programming apparatus 102. The schematic diagram 102 is representative of a small portion of a memory array of an EEPROM. The electrically alterable memory cell 100 is comprised of a select transistor 104 connected in series with a memory transistor 106. A drain input of the select transistor 104 is connected as an input to the electrically alterable memory cell 100. A source output of the memory transistor 106 is connected as an output to the electrically alterable memory cell 100.
The input to the electrically alterable memory cell 100 is connected to the bitline BL and the output of the electrically alterable memory cell 100 is connected to an array VSS AVSS—IN. A wordline WL_IN connects to a gate of the select transistor 104 and a sense line SL_IN connects to a gate of the memory transistor 106. The bitline BL may connect to a plurality of memory cells (not shown) like the electrically alterable memory cell 100. The plurality of cells is arranged to form an array of electrically alterable memory cells.
The bitline BL connects to a source output of a bitline-select transistor 108. A drain input of the bitline-select transistor 108 connects to a programming-voltage node VM—IN.
A bitline-coupling latch 110 is comprised of a pair of cross-coupled inverters forming a latch loop 112. Outputs of the latch loop 112 are a latch output Q and a complementary latch output Q. A source of power for the latch loop 112 is provided by the programming-voltage node VM—IN.
The latch loop is programmed to a logic level 0 by providing a low-resistance path through a series connection of a DATA transistor 114 and a Y-address transistor 116 from the latch output Q to ground. Complementary data are received at a DATA input DATA_IN of the DATA transistor 114 and Y-address information is received at a Y-address input YA—IN of the Y-address transistor 116. The latch loop 112 is programmed to a logic level 1 by providing a low-resistance path through a series connection of a set transistor 118 from a complementary latch output Q to ground. The latch loop 112 is programmed by applying a logic level 1 to the set input SET_IN of the set transistor 118. The complementary latch output Q connects to a gate input of the bitline-select transistor 108.
With reference to FIG. 1b, a waveform diagram of a prior art programming cycle 150 for an electrically alterable memory cell 100 (FIG. 1a) begins with a set pulse 152 of a set signal SET rising from 0 V (Volts) to 3 V during a SET-LATCH phase. The set pulse 152 is applied to the set input SET_IN (FIG. 1a) which causes the bitline-coupling latch 110 to store the logic level 1.
The SET-LATCH phase is followed by a LOAD phase in the programming cycle 150. In a LOAD phase a logic level 0 is set in the latch loop 112 (the complementary latch output Q is a logic level 1) when data are to be programmed into a memory cell. During the LOAD phase a DATA pulse 154 at a high logic level is applied to the DATA input DATA_IN and a Y-address pulse 156 at a high logic level is applied concurrently to the Y-address input YA—IN. Application of the DATA pulse 154 and the Y-address pulse 156 to the respective transistor-control inputs produces a low-resistance path through the DATA transistor 114 and the Y-address transistor 116 from the latch-loop output Q to ground and sets the latch loop 112 to a logic level 0 state.
The LOAD phase is followed by an ERASE phase. The programming voltage VM rises from 3 V to a 12 V level in a first high-voltage-programming pulse 158 in the ERASE phase. To erase the electrically alterable memory cell 100 a first wordline pulse 160 from 0 V to 12 V of the wordline signal WL is applied to the wordline WL_IN and a sense-line pulse 162 from 0 V to 12 V of the sense-line signal SL is applied to the sense line SL_IN.
Following the ERASE phase a WRITE phase contains a second high-voltage-programming pulse 164 that transitions from 3 V to 12 V and back to 3 V by the end of the WRITE phase. To select the electrically alterable memory cell 100 for programming, a second wordline pulse 166 from 0 V to 12 V and a second high-voltage-programming pulse 164 are applied.
The programming cycle 150 is normally followed by a READ operation. In the READ operation a connection of the bit line BL is provided to a sense amplifier (not shown) so that transistor 106 produces a current to be read by the sense amplifier.
During development of semiconductor fabrication processes, dimensions and features shrink from one generation to the next as a process is scaled down to achieve an increase in production efficiency. A first metal layer (metal-one) wiring pitch forms a limit for routing bitlines in a minimum area. Control of bitline coupling has dictated there be a latch per bit line for programming. Even with a scaling in layout, latches in a present generation of fabrication process take far more area than a corresponding set of bitlines being coupled to by the latches. Various orientations of latches as well as the use of a polysilicon layer for use in intra-cell connections has been tried as a solution to minimize the mismatch between a latch array and a minimum bitline routing pitch. Use of vias from metal-one to metal-two (second metal layer) has been considered; but a resultant metal-one wiring pitch is inefficient relative to a possible pitch available in the semiconductor process. Efforts with latch layout orientation, metal-one to metal-two vias, and the use of polysilicon have not been sufficient to solve an inefficiencies layout described.
A solution is needed that will allow the use of the tightest possible metal-one pitch that the fabrication process allows and simultaneously provide a lessening of the impact of having latch-based control of bitline coupling. Incorporation of the solution needs to be done in a manner transparent to the user and done in a way that can avoid the need to provide additional area to accommodate a latch beyond the area required for a minimum bitline pitch. Maintaining an optimal bitline pitch possible avoids low utilization of layout area for a latch-bitline combination and avoids having that inefficiency multiplied by the thousands of possible occurrences of the situation in a memory array.